FRANCAIS francophone2.gif ANGLAIS



Created the, 12/06/2019

 Updated the, 02/01/2020

Visiteurs N°  

Back to Main Sites New Blog Novelty Search engine Your Shopping Cart For Shopping Your Member Area Bookmarks, Your Favorite Games Static Welcome Page Site in French Web Site in English
Basic Electronics Fundamental Technology Test your Knowledge Digital Theoretical Electronics Digital Practical Electronics Digital Electronic Lexicon Data book TTL Data book CMOS TVC Troubleshooting Mathematical
Theoretical of Microcomputers Test your Knowledge Practical Microcomputers Computer Glossaries
The light Field of Action Electromagnetic Radiation
Classification of Resistances Identification of Resistances Classification of Capacitors Identification of Capacitors
Mathematical Forms
Geometry Physical 1. - Electronic 1. 2. - Electronic 1. 3. - Electrical 1. 4. - Electromagnetism
Access to all our Products
E. T. F. - Volume I - 257 Pages E. T. F. - Volume II - 451 Pages E. T. F. - Volume III - 611 Pages E. T. D. - Volume I - 610 Pages N. B. M. - Volume I - 201 Pages E. T. M. - Volume I - 554 Pages Business at Home Books 34 free pages Our E-books Geometry Software Electronic Components Software
Overview of all our Products
E. T. F. - Volume I - 257 Pages E. T. F. - Volume II - 451 Pages E. T. F. - Volume III - 611 Pages E. T. D. - Volume I - 610 Pages E. T. M. - Volume I - 554 Pages Geometry Software Electronic Components Software
Our Lessons in PDF Formats
Basic Electronics Fundamental Technology Digital Theoretical Electronics Digital Practical Electronics Theoretical of Microcomputers Mathematics
Data Processing
Troubleshooting Win98 and WinXP PC Troubleshooting Glossary HTML and Programs PHP and Programs JavaScript (in progress) Creation of several Sites
Electronic Forum and Infos Electronic Forum and Poetry
Miscellaneous and others
Form of the personal pages News XML Statistics CountUs JavaScript Editor Our Partners and Useful Links Partnership Manager Our MyCircle Partners Surveys 1st Guestbook 2nd Guestbook Site Directories

Signets : 
  Prepositionable counters        Large capacity meters       Footer

Counters - Countdown Counters - Prepositionable Counters :


So far, you have seen counters incrementing their content by one unit at each new impulse.

There are also counters that decrement their content. We then speak of down-counters.

The diagram of Figure 41 is a module down-counter 8 made with 3 flip-flops D. The timing diagram relating to its operation and the state diagram are also represented in this figure We can compare this diagram with that of Figure 12.


The first flip-flop is always wired as a divider by two since the LSB alternates from «0» to «1» in counting mode as in counting mode.

On the other hand, for the next two flip-flops, it is the output Q of the previous flip-flops which supplies the clock signal and not Q_barre.gif.

Figure 42 represents the diagram of a synchronous down-counter of module 8.


A combinatorial network composed of three gates is needed here.

Down-counters exist in the form of integrated circuits. These circuits operate either in counting mode or in counting mode. There are two types.

In the first type, there is only one control input of the up / down counting mode.

In the second type, there are two clock inputs ; one is relative to the counting mode, the other to the counting mode.

Figure 43 shows these two possibilities.

An example of an up / down counter (4029) will be presented in Chapter 6. 2.




In the component market, it is easy to find 2n or 10 module meters (usually n ³ 4).

On the other hand, for a counter having n states (n odd), it is necessary to resort to a combinational network, which increases the complexity of the circuit.

It is for this reason that manufacturers have developed pre-positioned meters.

These allow to limit the number of states that can take a counter, that is, they reduce the module.

For a pre-settable counter whose maximum module is 16, it will be possible to reduce this module between 2 and 16.

For this, these counters have as many prepositioning inputs as outputs. The diagram of Figure 44 represents such a counter.


The four inputs I1, I2, I3 and I4 are the prepositioning inputs.

CARRY is an exit of restraint or postponement. This output is at level H only when the four outputs Q1, Q2, Q3 and Q4 are at level H. Otherwise, it remains at level L.

The LOAD entry is a command entry. It makes it possible to «load» the counter in the logical state where the four prepositioning inputs are located.

If the loading is asynchronous, as soon as the LOAD input is at the level L, the logical state of I1 is transmitted to Q1, that of I2 to Q2 and so on ...

If the loading is synchronous, it is necessary first of all that the entry LOAD is at the level L (level active), then it is necessary to apply a pulse of clock for the loading is carried out.

By performing the wiring of Figure 45, it is possible to use the CARRY output to preposition the meter.


When the counter goes to state 15, the LOAD input goes to the L level and the loading takes place at the next clock edge (synchronous LOAD input).

The timing diagram of Figure 46 shows an example of operation with this arrangement.


The counter is prepositioned in state 13 and its module is 3 (states 13, 14 and 15).

With this type of assembly, it is possible to go from a predetermined state (here 13) to state 15 (in the case of a modulo counter 16), but this counter does not go through the states 0, 1, 2 ...

If one wants to start the counting phase starting from 0, it is necessary to carry out one of the two montages of Figure 47.


In Figure 47-a, when the output of the counter goes to 01012 = 510, the LOAD input goes to 0. So, at the next clock signal, the counter goes back to 0 since the four inputs prepositioning are wired to the ground (synchronous LOAD input).

It is also possible to use the CLEAR input as shown in Figure 47-b ; this CLEAR input is also synchronous.

In both cases, the NAND gate is used to detect the state of the counter so that it returns to 0.

However, this system is too rigid because it imposes a given combinational network to achieve a defined module counter. However, with a prepositionable counter, it is sufficient to change the data on the prepositioning entries to modify the module.

6. 2. - INTEGRATED METER HEF 4029B      [Return to Chapter 5]

It is a 4-bit binary / decimal synchronous counter / decounter realized in MOS technology.

Its block diagram and pinout are given in Figure 48.


The clock signal is applied to the CP input. It is the rising edges that are active. CE_barre.gif is a validation entry. If it is at level H, the counter is inhibited as well as the restraint. PL is the priority asynchronous parallel loading entry. As soon as it goes on level H, the four data present on P0, P1, P2 and P3 are transferred on the outputs O0, O1, O2 and O3.

The command UP / DN_barre.gif allows to count (UP / DN_barre.gif at level H), or to count down (UP / DN_barre.gif at level L).

The command BIN / DEC_barre.gif allows counting / down counting either in binary code (BIN / DEC_barre.gif at level H), or in decimal code (BIN / DEC_barre.gif at level L).

The output TC_barre.gif is normally at level H nd goes to level L when the counter reaches the maximum count counting count or the minimum countdown countdown mode provided that CE_barre.gif is at level L.

We will see in the following chapter the use that is made of this output TC_barre.gif.

The table in Figure 49 shows the different modes of operation of this meter.

Figure 49. - Counter operating table HEF 4029B.
PL BIN / DEC_barre.gif UP / DN_barre.gif CE_barre.gif CP MODE

Parallel loading

L X X H X Without change
L L L L decimal countdown
L L H L Decimal count
L H L L Binary countdown
L H H L Binary count

Overall, there are four modes of operation since there are two command entries (BIN / DEC_barre.gif and UP / DN_barre.gif) allowing four combinations.

The state diagrams in Figures 50 and 51 represent these four modes of operation.


In Figure 50, you may notice that if the counter is in a state between 10 and 15 (power-on case), it re-enters the state ring after a certain number of clock pulses. For example, from state 12, it goes to state 13 and then to state 4 in counting mode.

The timing diagram of Figure 52 illustrates the operation of this counter in decimal mode. The entry BIN / DEC_barre.gif is at level L.


At time t1, the command PL (loading of the counter) goes to the level L. So at the active clock edge that follows, the counting can begin.

CE_barre.gif is in state «0». The count is validated. The counter progresses from «0» at «9». As soon as it goes to «9» at time t2, the output TC_barre.gif (held) goes to level L.

During this state 9, the command entry UP / DN_barre.gif passes to level L, so the counter will go into countdown mode. Immediately, the output TC_barre.gif returns to level H since the counter is in countdown mode. At the next active clock edge, the counter goes to 8 and then to 7 ... to 0.

At time t3, the down-counter goes to «0» but the output TC_barre.gif remains at level H since the validation input CE_barre.gif has just passed to level H.

On the other hand, after a period of the clock signal, this entry CE_barre.gif passes to the level L and consequently the exit TC_barre.gif can pass to the level L.

At time t4, the command PL goes to level H so the counter is loaded and the latter goes to state «6».

It would be possible to draw the same type of timing diagram for the binary mode.



We can make two remarks :

      Firstly, by using individualized flip-flops, we are very quickly limited in the capacity of such a counter.

Indeed, it becomes necessary to use a large number of integrated circuits (flip-flops and combinatorial network).

      Then, existing counters in the form of integrated circuits hardly exceed a dozen stages (type 4040), therefore limit the capacity to 4095 = 212 - 1.

There are built-in counters with up to 24 stages (circuit 4521), but not all stages have an output. These circuits are generally used as dividers and not as counters.

For this reason, several counters are assembled together as shown schematically in Figure 53.


Simply connect the Q4 output of a counter (synchronous or asynchronous) of rank N to the clock input of the next counter (of rank N + 1). An inverter is interposed between this output Q4 and the clock input because it is active on the rising edge (in this case).

If each counter has a module equal to 16 (divisor by 16), the total module is equal to 16N, if N is the total number of counters.

On the Q4 output of the Nth counter, it is possible to collect a frequency signal :

Clock frequency / 16 N

For two counters in series, the module is 256 (16 x 16) and the clock signal is divided by 256.

Some meters have a CARRY output and two counter enable inputs (for example, CEP and CET).

If both of these inputs go to L, the counter hangs in the state it is in at that time.

These characteristics enable the assembly of Figure 54 to be carried out.


When the counter N° 1 reaches its maximum capacity, the output CARRY goes to the level H and consequently, to the active front of the clock which will follow, the counter N° 2 will be incremented (case of a counter) and the counter N° 1 will go to state «0». At this point, the CARRY output goes back to L level, which invalidates counter N° 2 again.

Counter N° 3 is incremented only if the CARRY outputs of the first two counters are at level H. At this time, the CEP input of counter N° 3 returns to level L, which invalidates it again and and so on ...

It should be noted that the CARRY output goes to H level only if the meter has reached its maximum capacity and if its CET input is at level H.

Thus, it is certain that a counter of rank N will increment only if all the counters which preceded it reached their maximum capacity.

With up / down counters having two clock inputs (one for counting mode, the other for down counting mode), a CARRY output and a BORROW output, it is possible to edit Figure 55.

The UP input is the counting input and the DOWN input is the counting input.


In counting mode, the operation is identical to that of the assembly of Figure 53.

In the present case, the output CARRY is active at 0. When the counter N° 1 is at the state 15, the output CARRY is at the level L. At the following clock edge, it returns to the level H and allows the incrementation of counter N° 2. The operation of the assembly is asynchronous.

In downcount mode, the BORROW (down countdown) output goes to L when the down counter reaches 0.

Thus, when a new active edge appears on the DOWN input of the counter N° 1, the latter returns to the state 15 and the output BORROW to the state «1», which decreases by one unit the counter N° 2.


By connecting several HEF 4029 B meters as shown in Figure 56, it is possible to obtain a high capacity counter / down counter.

The validation input CE_barre.gif of the first counter is wired to ground permanently.


Then, the output TC_barre.gif of each counter is connected to the entry CE_barre.gif of the following counter. Therefore, for a stage (a HEF 4029 B counter) of rank N to be incremented (decrement), its entry CE_barre.gif must be at the level L, so that the counter of rank N - 1 has reached its maximum capacity (in this case, the output TC_barre.gif passes to level L).

Moreover, in order for the output TC_barre.gif of the counter of rank N - 1 to be at the level L, it is also necessary that its entry CE_barre.gif is at the level L.

Therefore, for a counter of rank N to increment (decrement), all the counters that precede it must have reached their maximum capacity.

With this montage ends this theory on the counters.

The following theory will introduce you to decoding systems and displays.

  Click here for the next lesson or in the summary provided for this purpose.   Top of page
  Previous Page   Next Page

Nombre de pages vues, à partir de cette date : le 27 Décembre 2019

compteur visite blog gratuit

Mon audience Xiti

Send an email to Corporate Webmaster for any questions or comments about this Web Site.

Web Site Version : 11. 5. 12 - Web Site optimization 1280 x 1024 pixels - Faculty of Nanterre - Last modification : JANUARY 02, 2020.

This Web Site was Created on, 12 JUNE 2019 and has Remodeled, in JANUARY 2020.