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Internal Architecture of the Microprocessor :


3. - INTERNAL MICROPROCESSOR ARCHITECTURE


So far, the microprocessor has been examined externally, in its relationships with the surrounding circuits.

Now let's take a look at its internal structure. The previous lesson already introduced you to some internal parts : the ALU, the Accumulator and some registers.

In the simplified diagram, you have noticed that these assemblies were connected by internal buses. The number of these buses is an important element in the characterization of the internal structure.

3. 1. - SINGLE BUS STRUCTURE

Figure 16 represents a very simple structure : the data are stored in the registers R0 and R1 and are routed to the ALU on a single bus.


Structure_Interne_a_Bus_de_Donnees_Unique.GIF


The result of an operation is routed on the data bus to be stored in one of the registers.

The bus is therefore used for data entering and leaving the ALU.

Let us see the functioning of the set, assuming that the ALU adds the content of the registers R0 and R1 and puts the result in R0.

Figure 17 shows the first phase of the operation : the content of R0 which we will call Data 0 is transferred to the right input of the ALU and is temporarily stored in the accumulator.



The data stored in R0 is sent to the accumulator, following the hatched route. During this phase, R0 is connected to the bus.

In the second phase of the operation, the content of R1 which is Data 1, is transferred to the right input of the ALU (Figure 18).


Deuxieme_Phase_Addition.GIF


Each of these phases is controlled by one (or more) signal (s) from the microprocessor control circuit. This (these) signal (s) is synchronized by the system clock.

The ALU, which is only a combinational circuit, delivers the result of the addition almost instantaneously (propagation time inside the ALU.

The Figure 19 shows the end of the operation.


Phase_Finale_de_l_Addition.GIF


The result of the addition is transferred by the data bus to the register R0.

In fact, the operation is not carried out exactly this way.

Indeed, the result which is routed on the data bus is also directed towards the right input of the ALU. The accumulator is a register, so its content does not change.

The result is therefore added to the contents of the accumulator and the ALU thus generates a new result. The operation can thus be repeated indefinitely.

To resolve this problem, simply add a temporary register to the right entry of the ALU (Figure 20). This register is controlled by a specific signal.

Schema_Definitif_du_Microprocesseur.GIF

In addition, another register is added, called a temporary accumulator, which makes it possible to free the accumulator, so that the latter can store the result of the operation.

3. 2. - TWO BUS STRUCTURE

This structure shown in Figure 21 solves the problem encountered in the previous case.

Microprocesseur_a_deux_Bus.GIF 

The data bus routes the first operand to the accumulator, then the second to the right input of the ALU.

The result is routed on a second bus which is the results bus.

3. 3. - THREE BUS STRUCTURE

This structure is the fastest and most efficient. As shown in Figure 22, each register is connected to three buses.

Microprocesseur_a_3_Bus.GIF

There are two data buses (bus A and bus B), each connected to one of the inputs of the ALU. Thus, the two operands can be routed simultaneously to the ALU.

The third bus is obviously the results bus.

The loopback problem encountered in the single bus structure can only occur if the result generated by the ALU is immediately transferred to one of the inputs of the ALU (Figure 23).

Second_Registre_du_Microprocesseur.GIF

A loop is created since the result is sent again to input B of the ALU.

It is therefore necessary to add temporary registers as in the case of the single bus structure.

After examining the three possible structures, the following conclusions can be drawn :

Single bus systems have the advantage of requiring few links inside the microprocessor. Consequently, they occupy little space on the integrated circuit and are generally adopted in most microprocessors. However, they are slower since they require three phases per operation : the transfer of data from the first register to the ALU, then the transfer of the second data to the ALU and, finally, the storage of the result in the recipient register.

The microprocessors with several internal buses are faster, but they occupy more space on the integrated circuit. This multi-bus structure is generally adopted for bit slice processors (sliced processors).

To conclude, we can say that knowledge of the internal structure of a microprocessor is not essential for its use. However, this knowledge makes it possible to understand the differences in services offered by this or that microprocessor.

Test your knowledge of this 4th theory before continuing the other lessons by clicking here.


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