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  Offset register looped back on itself    Footer  

Logical Data Transmissions :



Suppose we want to transmit information (or data) about the state of four switches over a long enough distance.

The simplest idea is to use four wires and connect each one to an LED indicator as shown in Figure 21.


This solution is certainly the most convenient ; moreover, it has the merit of speed. Indeed, the state of each LED immediately indicates the position of the corresponding switch.

The transmission performed in this way is said to be parallel because the four pieces of information are simultaneously transmitted on four separate wires.

Parallel transmission, on the other hand, has the disadvantage of being expensive.

When the distance is great between the transmitter (represented here by the switches) and the receiver (represented by the LEDs), the connection wires become too long and the device too expensive especially and the information to be transmitted are numerous.

So we most often use the so-called serial transmission which uses only one link to transmit all the information.


If we resume the principle of the assembly shown in Figure 21, in a serial transmission, the information relating to the state of the switches are transmitted on the same line one after the other and no longer simultaneously on four separate lines.

To achieve this, we use a parallel-series shift register and we obtain the scheme of Figure 22.


The data transmission is carried out as follows :

In LOAD mode, we load the register with the information present on each of the inputs E1, E2, E3 and E4.

Then in SHIFT mode, four clock pulses make it possible to transmit on the serial output the four pieces of information after each other.

It should be noted that on the serial output is transmitted first information on the input E4.

Then come the information relating to the input E3, the input E2 and the input E1.

Figure 23 shows how the serial output of the register varies as a function of time and this for the example given in Figure 22. The serial input can be wired indifferently at the level H or at the level L.


In general, the information converted into series is not directly exploitable. Indeed, the data relating to each switch only lasts one clock period and there is therefore a problem of storage or storage of the data.

It comes to the idea of using a serial-parallel register on reception that has the inverse function of the transmission register.


Figure 24 shows how the transmit and receive registers are connected.


The serial output of the parallel-serial register is connected through the transmission line to the serial input of the serial-parallel register.

The clock pulses that control this last circuit can be the same as those of the first register.

They are then transmitted on another line. In this case, the transmission is said to be synchronous.

Only one clock generator is needed as shown in Figure 25.


If, on the other hand, the two registers are controlled by different clock signals, the transmission is said to be asynchronous.

In this case, the receiver circuit has its own clock generator as shown in Figure 26.


This is controlled by the signal transmitted on the line. Indeed, the clock generator of the receiver circuit must, in this case, deliver four synchronized clock pulses with the beginning of the transmission.

The advantage of asynchronous transmission compared to synchronous transmission is the economy of the line that transmits the clock signal.



Return to the parallel-serial register of Figure 22. Each load, the circuit stores the state of the parallel inputs E1, E2, E3 and E4, that is to say that of the switches.

When we apply pulses to the CLOCK input, the recorded information is transmitted to the observer next to the LED.

If however there is no clock pulse, the register keeps in memory, at least as long as it is powered, the information with which it has been loaded.

A register can therefore constitute a memory of several bits, four in the case of Figure 22.

However, there is a disadvantage when we perform offsets to transmit information to the LED.

Indeed, as the information is shifted, the one present at the output of the register is lost.

So after five pulses, the four pieces of information are lost.

If we do not want to keep the information or if on arrival there is a register that memorizes them, there is no problem.

On the other hand, if we want them not to be lost, we must realize the assembly of Figure 27.


The output of the register is connected to its input.

Thus, the information appearing at the output and which would be lost at each offset, is brought back to the input and is thus stored again.

We say, in this case, that the thus wired register rotates to the right of its contents.

To illustrate this mode of operation, suppose that the parallel-serial register in question is loaded with the data 0011.

Let us represent each flip-flop by a square inside which is written state (0 or 1).

Figure 28 shows the evolution of the contents of the register after each clock pulse.


We note that after four clock pulses, the register found the content it had just after loading.

Rotating the contents of a register to the right can also be done using a serial-serial register.


Figure 29 shows a series-series register looped back on itself through a combinatorial network similar to that of Figure 16.

The purpose of this network is to direct the input of the register, either the serial input or the serial output.


We find a new command entry called a loopback entry. When this is at level H, the serial input is connected to the register input through the network.

The circuit then behaves like a normal serial-serial register : the data present at the serial input is shifted to the right by one notch at each clock pulse.

When the loopback input is at the L level, however, the serial output of the register is connected to the input of the register through the network.

The circuit therefore behaves like a shift register looped back on itself.

It therefore rotates to the right of its contents at each clock pulse.

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