Sum in Parallel with Retention Series - The Summers :

1. 6. - SUM IN PARALLEL WITH RESTRAINT SERIES

Figure 13 shows an 8 bits parallel sum circuit with series hold.

We find that a parallel sum circuit requires as many full adders as there are numbers to add.

On the other hand, since the adopted output of an adder is connected to the input retained by the next, the summing circuit of Figure 13 is said to have a series hold. It should be noted that the selected input C0 of the first adder must be brought to state 0.

The parallel sum method is much faster than the serial sum method and the total time to perform the operation depends essentially on the time required for the carry propagation.

Indeed, even if all digits are summed simultaneously, the hold must propagate from the first to the last adder.

Thus, the result presented on the 8 outputs and on the C8 restraint will only be accurate when this propagation is done.

The mechanism of addition is as follows.

The first summator adds the two digits A0 and B0 and generates the sum S0 and the hold C1.

The second summator adds the numbers A1 and B1 with the hold C1 produced by the first summator. He can not add A1, B1 and C1 only when the retention C1 of the first sum will have been calculated by the first summator.

It is therefore necessary to wait a certain time for the containment to be propagated from floor to floor so that the sum S7 and the retention C8 are established (the sums S0 to S6 will already be established). Before this time, the result contained in S is not necessarily correct.

This mechanism, similar to that found in asynchronous counters, has the same advantage (simplicity of the circuit) and the same disadvantage (slowness).

The sum-in-parallel method with restraint propagation is, however, faster than that of the serial sum.

The time required for a complete adder to calculate the hold is very short, in the case of C-MOS circuits a few tens of nanoseconds.

However, the total time of the addition is the product of this time by the number of digits to be added.

It can not then be neglected especially in computers that must be able to make millions of additions per second. The holdback parallel sum method is used.

1. 7. - SUM IN PARALLEL WITH ANTICIPATED RETENTION

To sum up more quickly, you have to complicate the previous circuit.

It is based on the fact that the terms of the sum are known and available even before the addition operation begins. We can then calculate, in anticipation, the retention for each floor independently of the previous stages. It is a question of being able to have all the holdings simultaneously and in the shortest possible time.

In other words, the carry C1 must be calculated from the bits A0, B0 and C0, the carry C2 from the bits A0, B0, C0, A1 and B1 and so on.

Figure 14 shows the block diagram of a 4 bits adder with advance hold.

To calculate the deductions in advance, we must transform the equation of the retention Ci + 1 seen previously.

Ci + 1 = AiiCi + AiBi + iBiCi

Since Ci + 1 worth 1 when Ai = Bi = Ci = 1, we can add the terms AiBiCi to the expression of Ci + 1 as many times as we want (here 2 times).

• From where Ci + 1 = AiiCi + AiBiCi + AiBi + iBiCi + AiBiCi

•                     = AiCi (i + Bi) + AiBi + BiCi (i + Ai)

• Is Ci + 1  = AiCi + AiBi + BiCi

•                      = AiBi + Ci (Ai + Bi)

Posons : product AiBi = pi and sum Ai + Bi = Si

From where Ci + 1 = pi + CiSi

The expression of the restraint of the first floor becomes :

C1 = p0 + C0S0         

and the second floor :

C2 = p1 + C1S1